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HD74HC174
Hex D-type Flip-Flops (with Clear)
REJ03D0584-0300 Rev.3.00 Jan 31, 2006
Description
This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state.
Features
* * * * * * High Speed Operation: tpd (Clock to Q) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name HD74HC174P HD74HC174FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Abbreviation P -- EL (2,000 pcs/reel) ELL (2,000 pcs/reel) Taping Abbreviation (Quantity)
PRSP0016DH-B FP (FP-16DAV) PTSP0016JB-A HD74HC174TELL TSSOP-16 pin T (TTP-16DAV) Note: Please consult the sales office for the above package availability.
Function Table
Clear L H H H H High level Low level Irrelevant Inputs Clock X D X H L X X Output Q L H L no change no change
L
H: L: X:
Rev.3.00, Jan 31, 2006 page 1 of 7
HD74HC174
Pin Arrangement
Clear 1 1Q 2 1D 3 2D 4 2Q 5 3D 6 3Q 7 GND 8 (Top view)
Q CLR D CK Q CLR CK D
16 VCC 15 6Q 14 6D 13 5D 12 5Q 11 4D 10 4Q 9 Clock
D CK CLR Q
CK D CLR Q
D CK CLR Q
CK D CLR Q
Logic Diagram
Clock 1D Clear CK 2D D CL Q 2Q CK D CL 1Q
Q
CK 3D D CL
Q
3Q
CK 4D D CL
Q
4Q
CK 5D D CL
Q
5Q
CK 6D D CL
Q
6Q
Rev.3.00, Jan 31, 2006 page 2 of 7
HD74HC174
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 -65 to +150 Unit V V mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Note: Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Unit V V C ns Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 V Test Conditions
VIL
V
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
VOL
V
Vin = VIH or VIL
IOH = -4 mA IOH = -5.2 mA IOL = 20 A
Input current Quiescent supply current
Iin ICC
IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Rev.3.00, Jan 31, 2006 page 3 of 7
HD74HC174
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Ta = 25C Ta = -40 to +85C Unit Min Typ Max Min Max -- -- -- -- -- -- -- -- -- 100 20 17 5 5 5 25 5 4 80 16 14 -- -- -- -- -- -- -- -- 15 -- -- 17 -- -- 3 - -- 0 -- -- -1 -- -- 6 -- -- 5 -- 5 6 30 35 160 32 27 160 32 27 -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 -- -- -- -- -- -- -- -- -- 125 25 21 5 5 5 31 6 5 100 20 17 -- -- -- -- 5 24 28 200 40 34 200 40 34 -- -- -- -- -- -- -- -- -- -- -- -- 95 19 16 10 MHz Test Conditions
tPLH, tPHL
ns
Clock to Q
ns
Clear to Q
Setup time
tsu
ns
Data to Clock
Hold time
th
ns
Clock to Data
Removal time
trem
ns
Clear to Clock
Pulse width
tw
ns
Clock, Clear
Output rise/fall time Input capacitance
tTLH, tTHL
ns
Cin
pF
Test Circuit
Measurement point
CL*
Note: CL includes the probe and fig capacitance.
Rev.3.00, Jan 31, 2006 page 4 of 7
HD74HC174
Waveforms
* Waveform - 1
tr
90 % 90 % 50 % 10 % 50 %
tf VCC 0V th
Data
10 %
50 %
t su tr
th tf
90 %
t su
VCC
50 % 10 %
Clock
10 %
50 %
50 %
0V t PHL
90 % 50 % 10 %
tw t PLH
90 %
tw
VOH VOL
Q
50 % 10 %
t TLH
t THL
* Waveform - 2
90 % 50 % 10 %
tf
tr 90 % 50 % 10 % tw t rem t w(clock) 90 % 90 % 50 % 50 % 10 % t PHL tf t r t PLH 90 % 50 % 10 % t THL 50 % 10 % t TLH VOH VOL VCC 0V VCC 0V
Clear
Clock
Q
90 %
Note : Clock Input : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns Data Input : PRR 500 kHz
Rev.3.00, Jan 31, 2006 page 5 of 7
HD74HC174
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.3.00, Jan 31, 2006 page 6 of 7
HD74HC174
JEITA Package Code P-TSSOP16-4.4x5-0.65 RENESAS Code PTSP0016JB-A Previous Code TTP-16DAV MASS[Typ.] 0.05g
*1
D F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
16
9
bp
*2
HE
E
c
Reference Symbol
Dimension in Millimeters Min Nom 5.0 4.40 Max 5.3
Index mark
Terminal cross section ( Ni/Pd/Au plating )
D E A2 A1 0.03
0.07
0.10 1.10
1 Z e
*3
8 bp L1 x M
A bp b1 c c
1
0.15
0.20
0.25
0.10
0.15
0.20
A
HE
0 6.20 6.40 0.65
8 6.60
A1
L
e x y
0.13 0.10 0.65 0.4
1
y
Detail F
Z L L 0.5 1.0
0.6
Rev.3.00, Jan 31, 2006 page 7 of 7
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Keep safety first in your circuit designs!
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